Experience in digital hardware design and FPGA design using VHDL is essential.
Use of version control tools for FPGA development will be required.
Experience with Mentor Graphic and Clearcase tools is a plus.
Candidate should expect to work with engineers of various disciplines to translate
system performance and operational specifications into hardware requirements.
Candidate must have experience in allocating hardware requirements for implementation
via discrete circuits or FPGAs and have experience with PCB layouts of high
density for high speed digital design.
Candidates must be experienced at using both worst case and statistical design
methods to produce reliable designs which will operate in challenging environments.
Candidate should have experience at part selection with requirements for stressful
environments, DTUPC and obsolescence avoidance.
A good understanding of Databus, Datcom and Telecom protocols is needed in order
to quickly implement standard interfaces to other systems
Candidate must have a demonstrated ability to accomplish tasks on schedule
and within budget and will be able to document their performance using Raytheon’s
Earned Value Management System.
Candidate must be familiar with the hardware design process throughout the
development life cycle- Requirements Definition, Preliminary Design, Detailed
Design, Implementation, Integration, Test, Production and Field Support. Candidate
will be working in a world class CCMI Level 5 process environment and must be
able to practice defect containment, conduct peer reviews, and collect process
metrics including cost and schedule variances. Candidates will be expected to
use formal methods for making and documenting major design decisions. Candidates
will need to become proficient using Raytheon procedures and will be expected
to make suggestions for process improvement using tools such as Raytheon’s
version of Six Sigma.
Candidates should have experience in documenting their work using formal plans,
procedures, reports, computerized Bills Of Material, configuration managed drawings
and change control procedures.
Candidate must be experienced in using state of the art technical test equipment
( signal sources, logic analyzers, protocol analyzers, oscilloscopes) to test
and verify hardware designs.
Candidate must have extensive knowledge of FPGA design methodology and be well
versed with both front-end design, simulation, and verification CAD tools as
well as back-end physical implementation toolsets.
Candidate will be responsible for directing the efforts and mentoring of lower
level engineers and technicians.
Required Skills:
Digital logic design
PCB layout design
VHDL design
VHDL Simulation & Testbenches
Schematic capture (Cadence tool experience a plus)
Computer Aided Design (CAD) tools – Cadence, ProEngineer
Experience with Microsoft Office applications
Oral and written communication skills
Desired Skills:
Xilinx, Altera and Lattice FPGA Experience
Mentor Graphics ModelSim
Timing Designer
Clearcase
Six Sigma
MATLAB
MathCAD
Pspice
Signal integrity analysis
JTAG and Boundary Scan tools
Current DoD Secret Clearance
Required Education:
BS in Electrical Engineering
MS in Electrical Engineering preferred
Raytheon is an equal opportunity employer and considers qualified applicants
for employment without regard to race, color, creed, religion, national origin,
sex, sexual orientation, gender identity and expression, age, disability, or
Vietnam era, or other eligible veteran status, or any other protected factor.
To Apply for this position, please CLICK HERE
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